Generally, in the early stage of powering a circuit system, when the power supply voltage does not reach a stable expected state, the voltage and the logic state of many circuit components (such as semiconductor devices or the like) and circuit nodes are instable. To make the circuit system start the operation from the state expected by the designer after being powered each time, a Power-On-Reset (POR) circuit may be utilized during a certain period of time after the power supply is stable. The reset signal can force the circuit system to stay in the initial state expected by the designer. After the validity period of the reset signal expires, the circuit system starts the operation from the expected initial state. Namely, the POR circuit can make reset operations on other modules in the circuit system, to eliminate the instability of the circuit module in the initialization of the power-on.
In the related art, there have been various POR circuits, but they have large power consumption and instable performance. For example, FIG. 1 illustrates a schematic diagram of a POR circuit according to the related art. As shown in FIG. 1, the charge stored in the capacitor C1 is discharged to the power supply VDD through the resistor R1. Since values of both the resistor R1 and the capacitor C1 are relatively large, it takes a relatively long time to discharge completely the charge stored in the capacitor C1. If the power supply VDD is quickly powered on again immediately after previous power on failure, then the charge stored in the capacitor C1 cannot be discharged completely, and as a result, the voltage of the node 103 is relatively high, thus the square wave shaping circuit 101 always outputs high level and the POR signal POR1 cannot be generated effectively. Namely, when the power on is too slow to exceed the RC charging constant, the node 103 serves as the VDD all the time, so that POR signals cannot be generated correctively. In practical application, the power-on speed may range from 1 us to 10 ms, or be even more. In order to deal with the power-on with a speed of 10 ms or slower, large resistance or capacitance is needed to increase the product of RC (a large product of RC means long reset time).
It is thus clear that, in the above related art, due to the uncertainty of the rising speed of the power supply VDD, there is no guarantee that POR signals can be effectively generated in the circuit system in all cases, so the performance is unreliable.